DS90UB913A-Q1 Datasheet, PDF (14/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
www.ti.com
7.9 Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
t_LHT
CML Low-to-High
Transition Time
R_L = 100 Ω (Figure 3)
t_HLT
CML High-to-Low
Transition Time
R_L = 100 Ω (Figure 3)
t_DIS
Data Input
Setup to PCLK
2
Serializer Data Inputs (Figure 8)
t_DIH
Data Input
Hold from PCLK
2
t_PLD
Serializer PLL Lock
Time ^{(1) (2)}
R_L = 100 Ω (Figure 9)
t_SD
Serializer Delay⁽²⁾
R_T = 100 Ω, 10–bit mode
Register 0x03h b[0] (TRFB = 1) (Figure 10)
R_T = 100 Ω, 12–bit mode
Register 0x03h b[0] (TRFB = 1) (Figure 10)
32.5T
11.75T
t_JIND
Serializer Output
Deterministic Jitter
(3) (4) (5)
Serializer output intrinsic deterministic jitter.
Measured (cycle-cycle) with PRBS-7 test pattern
NOM
150
150
1
38T
13T
0.13
MAX
330
UNIT
ps
330
ps
ns
ns
2
ms
44T
ns
15T
ns
UI
t_JINR
t_JINT
Serializer Output
Random Jitter ^(3)(4)(5)
Peak-to-peak Serializer
Output Jitter ^(3)(4)(5)
Serializer Jitter
λ_STXBW Transfer Function
-3 dB Bandwidth
δ_STX
Serializer Jitter
Transfer Function
(Peaking)
δ_STXf
Serializer Jitter
Transfer Function
(Peaking Frequency)
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
Serializer output peak-to-peak jitter includes
deterministic jitter, random jitter, and jitter transfer
from serializer input. Measured (cycle-cycle) with
PRBS-7 test pattern.
10–bit mode
PCLK = 100 MHz. Default Registers
12–bit high frequency mode
PCLK = 75 MHz. Default Registers
12–bit low frequency mode
PCLK = 50 MHz. Default Registers
10–bit mode
PCLK = 100 MHz. Default Registers
12–bit high frequency mode
PCLK = 75 MHz. Default Registers
12–bit low frequency mode
PCLK = 50 MHz. Default Registers
10–bit mode
PCLK = 100 MHz. Default Registers
12–bit high frequency mode
PCLK = 75 MHz. Default Registers
12–bit low frequency mode
PCLK = 50 MHz. Default Registers
0.04
0.396
2.20
2.20
2.20
1.06
1.09
1.16
400
500
600
UI
UI
MHz
dB
kHz
(1) t_PLD and t_DDLT are the times required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is verified by design.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, T_A = 25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
(4) Specification is verified by characterization and is not tested in production.
(5) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 x 28 )
12-bit HF mode: 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 )
12-bit LF mode: 1 UI = 1 / ( PCLK_Freq. x 28 )
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