DS90UB913A-Q1 Datasheet, PDF (34/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
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Register Maps (continued)
Table 6. DS90UB913A-Q1 Control Registers⁽¹⁾ (continued)
Addr
(Hex)
0x2D
0x2E -
0x34
0x35
Name
Inject Forward
Channel Error
PLL Clock
Overwrite
Bits Field
7
Force Forward
Channel Error
6:0 Force BIST Error
7:4 RSVD
PIN_LOCK to
3 External
Oscillator
2 RSVD
1
LOCK to External
Oscillator
0 LOCK2OSC
R/W
Default
RW
0
RW
0x00'h
Reserved.
RW
0
RW
0
RW
1
Description
1: Forces 1 (one) error over forward channel frame in
normal operating mode. Self clearing bit.
0: No error.
N: Forces N number of errors in BIST mode. This
register MUST be set BEFORE BIST mode is enabled.
BIST Error Count Register on the deserializer (i.e.
0x25 on 914A device) should be read AFTER BIST
mode is disabled for the correct number of errors
incurred while in BIST mode.
0: No error.
Reserved.
Status of mode select pin.
1: Indicates External Oscillator mode is selected by
mode-resistor.
0: External Oscillator mode is not selected by mode-
resistor.
Reserved.
Affects only when 0x03[1]=1 (OV_CLK2PLL) and
0x35[0]=0.
1: Routes GPO3 directly to PLL.
0: Allows PLL to lock to PCLK.
Affects only when 0x03[1]=1 (OV_CLK2PLL).
1: Allows internal OSC clock to feed into PLL.
0: Allows PLL to lock to either PCLK or external clock
from GPO3.
34
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