DS90UB913A-Q1 Datasheet, PDF (25/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

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DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
8.5 Programming
8.5.1 Programmable Controller
An integrated I2C slave controller is embedded in the DS90UB913A-Q1 Serializer. It must be used to configure
the extra features embedded within the programmable registers or it can be used to control the set of
programmable GPIOs.
8.5.2 Description of Bidirectional Control Bus and I2C Modes
The I2C-compatible interface allows programming of the DS90UB913A-Q1, DS90UB914A-Q1, or an external
remote device (such as image sensor) through the bidirectional control channel. Register programming
transactions to/from the DS90UB913A-Q1/914A-Q1 chipset are employed through the clock (SCL) and data
(SDA) lines. These two signals have open drain I/Os and both lines must be pulled-up to V_DDIO by an external
resistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them high when
they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by
releasing the output and allowing it to be pulled-up externally. The appropriate pullup resistor values will depend
upon the total bus capacitance and operating speed. The DS90UB913A I2C bus data rate supports up to 400
kbps according to I2C fast mode specifications.
For further description of general I2C communication, please refer to application note Understanding the I2C Bus
(SLVA704). For more information on choosing appropriate pullup resistor values, please refer to application note
I2C Bus Pullup Resistor Calculation (SLVA689).
Bus Activity:
Master
SDA Line S
Slave
Address
7-bit Address 0
Register
Address
Data
P
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 20. Write Byte
Bus Activity:
Master
Slave
Address
Register
Address
Slave
Address
SDA Line S
7-bit Address 0
S
7-bit Address 1
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 21. Read Byte
Data
N
A
C
K
P
SDA
SCL
START
MSB
1
7-bit Slave Address
2
6
LSB
ACK
R/W
Direction
Bit
Acknowledge
from the Device
MSB
7
8
9
1
Data Byte
2
LSB N/ACK
*Acknowledge
or Not-ACK
8
9
Repeated for the Lower Data Byte
and Additional Data Transfers
STOP
Figure 22. Basic Operation
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