DS90UB913A-Q1 Datasheet, PDF (40/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
www.ti.com
9.2.2.2 Detailed Design Procedure
Figure 35 shows a typical connection of a DS90UB913A-Q1 Serializer using an STP interface.
VDDIO
C8
C3
LVCMOS
Parallel
Bus
1.8 V
10 kQ
RID
DS90UB913A-Q1
VDDIO
VDDT
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
HS
VS
PCLK
MODE
VDDPLL
VDDCML
VDDD
DOUT+
DOUT-
1.8 V
C4
C9
C13
1.8 V
C5 C10
C14 _FB1
1.8 V
C6 C11 C15
FB2 _{1.8 V}
C7 C12
C1
C2
1.8 V
Serial
FPD-Link III
Interface
I2C
Bus
Interface
LVCMOS
Control
Interface
GPO
Control
Interface
FB3
FB4
Optional
VDDIO
PDB
GPO[0]
GPO[1]
GPO[2]
GPO[3]
RPU
C16
RPU
SCL
SDA
C17
Optional
ID[X]
RES
DAP (GND)
10 kQ
RID
NOTE:
C1 - C2 = 0.1 µF (50 WV)
C3 ± C7 = 0.01 µF
C8 - C12 = 0.1 µF
C13 - C14 = 4.7 µF
C15 = 22 µF
C16 - C17 = >100 pF
RPU = 1 kQ to 4.7 kQ
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 kQ (@ 100 MHz)
low DC resistance (<1 Q)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 35. DS90UB913A-Q1 Typical Connection Diagram — Pin Control (STP)
9.2.2.3 Application Curves
Time (200 ps/DIV)
Figure 36. STP Eye Diagram at 1.4-Gbps Line Rate (100-
MHz Pixel Clock) from Deserializer CML Loop-through
Output (CMLOUT±)
Time (2.5 ns/DIV)
Figure 37. STP Eye Diagram with 100-MHz TX Pixel Clock
Overlay from Deserializer CML Loop-through Output
(CMLOUT±)
40
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