DS90UB913A-Q1 Datasheet, PDF (2/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions ......................... 4
7 Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information .................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Recommended Serializer Timing For PCLK .......... 10
7.7 AC Timing Specifications (SCL, SDA) - I2C-
Compatible ............................................................... 11
7.8 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C-Compatible ................................. 11
7.9 Serializer Switching Characteristics........................ 14
7.10 Typical Characteristics .......................................... 15
8 Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 20
8.5 Programming .......................................................... 25
8.6 Register Maps ......................................................... 29
9 Application and Implementation ........................ 35
9.1 Application Information............................................ 35
9.2 Typical Applications ................................................ 37
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 42
11.1 Layout Guidelines ................................................. 42
11.2 Layout Example .................................................... 43
12 Device and Documentation Support ................. 45
12.1 Documentation Support ........................................ 45
12.2 Community Resources.......................................... 45
12.3 Trademarks ........................................................... 45
12.4 Electrostatic Discharge Caution ............................ 45
12.5 Glossary ................................................................ 45
13 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
Changes from Revision B (December 2014) to Revision C
Page
• Split document into two separate documents for parts DS90UB913A-Q1 and DS90UB914A-Q1. ...................................... 1
• Modified Automotive Features ............................................................................................................................................... 1
• Updated pin description for DIN to include active/inactive outputs corresponding to MODE setting..................................... 4
• Added pin description to GPO pins to leave open if unused. ................................................................................................ 5
• Changed Air Discharge ESD Rating (IEC61000-4-2: RD = 330 Ω, CS = 150 pF) to minimum ±25000 V. .......................... 6
• Added RTV text to Thermal Information table ........................................................................................................................ 7
• Added GPO[3:0] typical pin capacitances. ............................................................................................................................ 7
• Changed Differential Output Voltage minimum specification. ............................................................................................... 8
• Changed Single-Ended Output Voltage minimum specification............................................................................................. 8
• Added Back Channel Differential Input Voltage minimum specification................................................................................. 8
• Added Back Channel Single-Ended Input Voltage minimum specification. ........................................................................... 8
• Updated IDDT for V_{DD_n}=1.89V, V_DDIO=3.6V, RL=100Ω, Random Pattern with f=100 MHz, 10-bit mode to typical
value of 65 mA; value is currently 54 mA............................................................................................................................... 9
• Updated IDDT for V_{DD_n}=1.89V, V_DDIO=3.6V, RL=100Ω, Random Pattern with f=75 MHz, 12-bit high freq mode to
typical value of 64 mA; value is currently 54 mA.................................................................................................................... 9
• Updated IDDT for V_{DD_n}=1.89V, V_DDIO=3.6V, RL=100Ω, Random Pattern with f=50 MHz, 12-bit low freq mode to
typical value of 63 mA; value is currently 54 mA. ................................................................................................................. 9
• Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added footnote
and nominal clock period to be in terms of 'T'.⁽⁵⁾.................................................................................................................. 10
• Deleted Revised jitter freq. test conditions to be > f/20 and also updated typical values for t_jit0and t_jit2. ............................. 10
• Updated V_OL Output Low Level row with revised I_OL currents and max V_OL voltages, dependent upon V_DDIO voltage. ...... 11
• Updated Figure 2 title to state ‘“Worst-Case” Test Pattern for Power Consumption’. ......................................................... 12
• Added footnote that states the following: “UI – Unit Interval is equivalent to one serialized data bit width. The UI
scales with PCLK frequency.” Add below calculations to footnote. 12-bit LF mode 1 UI = 1 / ( PCLK_Freq. x 28 ) 12-
bit HF mode 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 ) 10-bit mode 1 UI = 1 / ( PCLK_Freq. /2 x 28 ) ..................................... 14
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