DS90UB913A-Q1 Datasheet, PDF (17/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

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DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
8.3 Feature Description
8.3.1 Serial Frame Format
The High Speed Forward Channel is composed of 28 bits of data containing video data, sync signals, I2C and
parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,
balanced and scrambled. The 28-bit frame structure changes in the 12-bit low frequency mode, 12-bit high
frequency mode and the 10-bit mode internally and is seamless to the customer. The bidirectional control
channel data is transferred over the single serial link along with the high-speed forward data. This architecture
provides a full duplex low speed forward and backward path across the serial link together with a high speed
forward channel without the dependence on the video blanking phase.
8.3.2 Line Rate Calculations for the DS90UB913A/914A
The DS90UB913A-Q1 device divides the clock internally by divide-by-1 in the 12-bit low frequency mode, by
divide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high frequency mode. Conversely, the
DS90UB914A-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus
the maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used to
calculate the maximum line rate in the different modes:
• For the 12-bit low frequency mode, Line rate = f_PCLK*28; for example, f_PCLK = 50 MHz, line rate = 50*28 = 1.4
Gbps
• For the 12-bit high frequency mode, Line rate = f_PCLK*(2/3)*28; for example, f_PCLK = 75 MHz, line rate =
(75)*(2/3)*28 = 1.4 Gbps
• For the 10-bit mode, Line rate = f_PCLK/2*28; for example, f_PCLK = 100 MHz, line rate = (100/2)*28 = 1.4 Gbps
8.3.3 Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following signals:
• Bidirectional control channel data across the serial link
• Parallel video/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 cyclic redundancy check (CRC) bits on the back
channel for error detection purposes. The DS90UB913A/914A chipset checks the forward and back channel
serial links for errors and stores the number of detected errors in two 8-bit registers in the Serializer and the
Deserializer respectively.
To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the DS90UB914A. If there is
a loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error on
the forward channel, the PASS pin will go low.
To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer.
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