DS90UB913A-Q1 Datasheet, PDF (39/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

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9.2.1.3 Application Curves
DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
Time (200 ps/DIV)
Figure 32. Coax Eye Diagram at 1.4-Gbps Line Rate (100-
MHz Pixel Clock) from Deserializer CML Loop-through
Output (CMLOUT±)
Time (2.5 ns/DIV)
Figure 33. Coax Eye Diagram with 100-MHz TX Pixel Clock
Overlay from Deserializer CML Loop-through Output
(CMLOUT±)
9.2.2 STP Application
Image
Sensor
Camera Data
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
DS90UB913AQ
Serializer
FPD-Link III
DS90UB914AQ
Deserializer
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
PCLK
DOUT+
RIN+
DOUT-
RIN-
Bi-Directional
Control Channel
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
PCLK
Camera Data
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
ECU Module
Camera Unit
4
GPO[3:0]
SDA
SCL
GPO[3:0]
SDA
SCL
GPIO[3:0]
SDA
SCL
4
GPIO[3:0]
SDA
SCL
Figure 34. STP Application Block Diagram
Microcontroller
9.2.2.1 Design Requirements
For the typical STP design applications, use the following as input parameters
Table 9. STP Design Parameters
DESIGN PARAMETER
V_DDIO
V_{DD_n}
AC Coupling Capacitors for DOUT±
PCLK Frequency
EXAMPLE VALUE
1.8 V, 2.8 V, or 3.3 V
1.8 V
0.1 µF
50 MHz (12-bit low frequency), 75 MHz (12-bit high frequency), 100
MHz (10-bit)
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