DS90UB913A-Q1 Datasheet, PDF (37/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

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DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
9.1.3 AC Coupling
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 28. For applications utilizing single-ended 50-Ω coaxial cable, the unused data pin (DOUT–, RIN–) should
utilize a 0.047-µF capacitor and should be terminated with a 50-Ω resistor.
SER
D_OUT+
D_OUT-
R_IN+
R_IN-
DES
Figure 28. AC-Coupled Connection (STP)
SER
D_OUT+
R_IN+
DES
D_OUT-
50Q
50Q
R_IN-
Figure 29. AC-Coupled Connection (Coaxial)
For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 0.1-
µF AC coupling capacitors to the line.
9.1.4 Transmission Media
The DS90UB913A/914A chipset is intended to be used in a point-to-point configuration through a shielded
coaxial cable. The Serializer and Deserializer provide internal termination to minimize impedance discontinuities.
The interconnect (cable and connectors) should have a differential impedance of 100 Ω, or a single-ended
impedance of 50 Ω. The maximum length of cable that can be used is dependent on the quality of the cable
(gauge, impedance), connector, board(discontinuities, power plane), the electrical environment (for example,
power stability, ground noise, input clock jitter, PCLK frequency, etc). The resulting signal quality at the receiving
end of the transmission media may be assessed by monitoring the differential eye opening of the serial data
stream. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pins.
Please refer to Cable Requirements for the DS90UB913A & DS90UB914A or contact TI for a channel
specification regarding cable loss parameters and further details on adaptive equalizer loss compensation.
9.2 Typical Applications
9.2.1 Coax Application
Image
Sensor
Camera Unit
Camera Data
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
4
GPO[3:0]
SDA
SCL
DS90UB913AQ
Serializer
FPD-Link III
DS90UB914AQ
Deserializer
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
PCLK
DOUT+
RIN+
DOUT- _50Q
50Q
RIN-
Bi-Directional
Control Channel
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
PCLK
GPO[3:0]
GPIO[3:0]
SDA
SCL
SDA
SCL
Camera Data
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
4
GPIO[3:0]
SDA
SCL
Figure 30. Coax Application Block Diagram
ECU Module
Microcontroller
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