DS90UB913A-Q1 Datasheet, PDF (33/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

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DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
Register Maps (continued)
Table 6. DS90UB913A-Q1 Control Registers⁽¹⁾ (continued)
Addr
(Hex)
0x10
Name
I2C Control
Bits Field
7 RSVD
6:4 SDA Hold Time
3:0 I2C Filter Depth
0x11 SCL High Time 7:0 SCL High Time
0x12 SCL LOW Time 7:0 SCL Low Time
0x13
General Purpose
Control
7:0 GPCR[7:0]
7:3 RSVD
0x14
BIST Control
2:1 Clock Source
0x15 -
0x1D
0 RSVD
0x1E
BCC Watchdog
Control
0x1F -
0x29
0x2A
0x2B -
0x2C
CRC Errors
7:1
BCC Watchdog
Timer
0
BCC Watchdog
Timer Disable
7:0
BIST Mode CRC
Errors Count
R/W
Default Description
Reserved.
Internal SDA Hold Time. This field configures the
RW
0x1'h
amount of internal hold time provided for the SDA
input relative to the SCL input. Units are 50 ns.
I2C Glitch Filter Depth. This field configures the
RW
0x7'h
maximum width of glitch pulses on the SCL and SDA
inputs that will be rejected. Units are 10 ns.
I2C Master SCL High Time This field configures the
high pulse width of the SCL output when the Serializer
is the Master on the local I2C bus. Units are 50 ns for
RW
0x82'h
the nominal oscillator clock frequency. The default
value is set to provide a minimum (4 µs + 1 µs of rise
time for cases where rise time is very fast) SCL high
time with the internal oscillator clock running at 26
MHz rather than the nominal 20 MHz.
I2C SCL Low Time This field configures the low pulse
width of the SCL output when the Serializer is the
Master on the local I2C bus. This value is also used as
the SDA setup time by the I2C Slave for providing
data prior to releasing SCL during accesses over the
RW
0x82'h Bidirectional Control Channel. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to provide a minimum (4.7 µs + 0.3 µs of fall time
for cases where fall time is very fast) SCL low time
with the internal oscillator clock running at 26MHz
rather than the nominal 20MHz.
RW
0x00'h
1: High.
0: Low.
Reserved.
Allows choosing different OSC clock frequencies for
forward channel frame.
OSC Clock Frequency in Functional Mode when OSC
RW
0x0'h
mode is selected or when the selected clock source is
not present, for example, missing PCLK/ External
Oscillator. See Table 2 for oscillator clock frequencies
when PCLK/ External Clock is missing.
Reserved.
Reserved.
The watchdog timer allows termination of a control
RW
0x7F'h
(111_1111'b)
channel transaction if it fails to complete within a
programmed amount of time. This field sets the
Bidirectional Control Channel Watchdog Timeout value
in units of 2 ms. This field should not be set to 0.
RW
0
1: Disables BCC Watchdog Timer operation.
0: Enables BCC Watchdog Timer operation.
Reserved.
R
0x00'h
Number of CRC Errors in the back channel when in
BIST mode.
Reserved.
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