DS90UB913A-Q1 Datasheet, PDF (16/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
8 Detailed Description
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8.1 Overview
The DS90UB913A-Q1 is optimized to interface with the DS90UB914A-Q1 using a 50-Ω coax interface. The
DS90UB913A-Q1 will also work with the DS90UB914A-Q1 using an STP interface.
The DS90UB913A/914A FPD- Link III chipsets are intended to link mega-pixel camera imagers and video
processors in ECUs. The Serializer/Deserializer chipset can operate from 25 MHz to 100 MHz pixel clock
frequency. The DS90UB913A-Q1 device transforms a 10/12-bit wide parallel LVCMOS data bus along with a
bidirectional control channel control bus into a single high-speed differential pair. The high speed serial bit stream
contains an embedded clock and DC-balanced information which enhances signal quality to support AC
coupling. The DS90UB914A-Q1 device receives the single serial data stream and converts it back into a 10/12-
bit wide parallel data bus together with the control channel data bus. The DS90UB913A/914A chipsets can
accept up to:
• 12-bits of DATA + 2 bits SYNC for an input PCLK range of 25 MHz to 50 MHz in the 12-bit low frequency
mode. Note: No HS/VS restrictions (raw).
• 12-bits of DATA + 2 SYNC bits for an input PCLK range of 37.5 MHz to 75 MHz in the 12-bit high frequency
mode. Note: No HS/VS restrictions (raw).
• 10-bits of DATA + 2 SYNC bits for an input PCLK range of 50 MHz to 100 MHz in the 10-bit mode. Note:
HS/VS restricted to no more than one transition per 10 PCLK cycles.
The DS90UB913A/914A chipset offer customers the choice to work with different clocking schemes. The
DS90UB913A/914A chipsets can use an external oscillator as the reference clock source for the PLL (see
section DS90UB913A/914A Operation with External Oscillator as Reference Clock) or PCLK from the imager as
primary reference clock to the PLL (see section DS90UB913A/914A Operation with Pixel Clock from Imager as
Reference Clock).
8.2 Functional Block Diagram
10 or
12
DIN
HSYNC
VSYNC
4
GPO[3:0]
PCLK
PLL
Clock
Gen
R_T
R_{T DOUT+}
RIN0+ ^RT ^RT
DOUT-
RIN0-
RIN1+
CDR
Clock
Gen
PDB
Timing and
Control
SDA
SCL
ID[x]
MODE
DS90UB913AQ - SERIALIZER
RIN1-
PDB
BISTEN
OEN
SEL
MODE
Timing and
Control
DS90UB914AQ - DESERIALIZER
10
or
12
ROUT
HSYNC
VSYNC
4
GPIO[3:0]
PCLK
LOCK
PASS
SDA
SCL
IDx[0]
IDx[1]
16
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