DS90UB913A-Q1 Datasheet, PDF (4/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
5 Device Comparison Table
PART NUMBER
DS90UB913Q-Q1
DS90UB913A-Q1
FPD-III FUNCTION
Serializer
Serializer
PACKAGE
WQFN RTV (32)
WQFN RTV (32)
6 Pin Configuration and Functions
32-Pin WQFN
Package RTV
Top View
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TRANSMISSION MEDIA
STP
Coax or STP
PCLK FREQUENCY
10 to 100 MHz
25 to 100 MHz
VDDIO
DIN[6]
DIN[7]
VDDD
DIN[8]
DIN[9]
DIN[10]
DIN[11]
24 23 22 21 20 19 18
17
DAP = GND
DS90UB913A-Q1
Serializer
1
2
3
4
5
6
7
8
GPO[1]
GPO[0]
VDDCML
DOUT+
DOUT-
VDDT
VDDPLL
PDB
Pin Functions: DS90UB913A-Q1 Serializer
PIN
I/O
NAME
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
DIN[0:11]
19,20,21,22,
23,24,26,27,
29,30,31,32
Inputs,
LVCMOS
w/ pulldown
Parallel Data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] are
inactive and should not be used. Any unused inputs (including DIN[10:11]) should be No
Connect. For 12-bit MODE (HF or LF), parallel inputs DIN[0:11] are active. Any unused
inputs should be No Connect.
HSYNC
1
Input,
LVCMOS
w/ pulldown
Horizontal SYNC Input. Note: HS transition restrictions: 1. 12-bit Low-Frequency mode: No
HS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions (raw) 3. 10-bit
mode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open if
unused.
VSYNC
2
Input,
LVCMOS
w/ pulldown
Vertical SYNC Input. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode: No VS
restrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3. 10-bit High-
Frequency mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave
open if unused.
PCLK
Input,
3
LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pulldown
4
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