DS90UB913A-Q1 Datasheet, PDF (19/51 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Serializer

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DS90UB913A-Q1
SNLS443C – MAY 2013 – REVISED APRIL 2016
Feature Description (continued)
8.3.5 General Purpose I/O (GPIO) Descriptions
There are 4 GPOs on the Serializer and 4 GPIOs on the Deserializer when the DS90UB913A/914A chipsets are
run off the pixel clock from the imager as the reference clock source. The GPOs on the Serializer can be
configured as outputs for the input signals that are fed into the Deserializer GPIOs. In addition, the GPOs on the
Serializer can behave as outputs of the local register on the Serializer. The GPIOs on the Deserializer can be
configured to be the input signals feeding the GPOs (configured as outputs) on the Serializer. In addition the
GPIOs on the Deserializer can be configured to behave as outputs of the local register on the Deserializer. The
DS90UB913A Serializer GPOs cannot be configured as inputs for remote communication with Deserializer. If the
DS90UB913A/914A chipsets are run off the external oscillator source as the reference clock, then GPO3 on the
Serializer is automatically configured to be the input for the external clock and GPO2 is configured to be the
output of the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 and
GPIO3 on the Deserializer can only behave as outputs of the local register on the Deserializer. The GPIO
maximum switching rate is up to 66 kHz when configured for communication between Deserializer GPIO to
Serializer GPO.
8.3.6 LVCMOS V_DDIO Option
1.8-V/2.8-V/3.3-V Serializer inputs are user configurable to provide compatibility with 1.8-V, 2.8-V and 3.3-V
system interfaces.
8.3.7 Pixel Clock Edge Select (TRFB / RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 14. Programmable PCLK Strobe Select
8.3.8 Power Down
The SER has a PDB input pin to ENABLE or power down the device. Enabling PDB on the SER will disable the
link to save power. If PDB = HIGH, the SER will operate at its internal default oscillator frequency when the input
PCLK stops. When the PCLK starts again, the SER locks to the valid input PCLK and transmit the data to the
DES. When PDB = LOW, the high-speed driver outputs are static HIGH. Please refer to Power-Up Requirements
and PDB Pin for power-up requirements.
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