SMJ34020A Datasheet, PDF (9/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
architecture (continued)
register files
Boolean, arithmetic, pixel-processing, byte, and field-move instructions operate on data within the
general-purpose register files. The SMJ34020A contains two register files of fifteen 32-bit registers and a
system stack pointer (SP). The SP is addressed in both register file A and register file B as a sixteenth register.
Transfers between registers and memory are facilitated using a complete set of field move instructions with
selectable field sizes.
The 15 general-purpose registers in register file A are used for high-level language support and
assembly-language programming. The 15 registers in register file B are dedicated to special functions during
PIXBLTS and other pixel operations but can be used as general-purpose registers at other times.
stack pointer (SP)
The stack pointer is a dedicated 32-bit internal register that points to the top of the system stack.
program counter (PC)
The SMJ34020A’s 32-bit program counter register points to the next instruction-stream word to be fetched.
Since instruction words are aligned to 16-bit boundaries, the four LSBs of the PC are always zero.
instruction cache
An on-chip cache contains 512 bytes of RAM and provides unimpeded access to instructions. The cache
operates automatically and is transparent to software. The cache is divided into four 128-byte segments.
Associated with each segment is a 22-bit segment start address register (SSA) to identify the addresses in
memory corresponding to the current contents of the cache segment. Each cache segment is further partitioned
into eight subsegments of four long words (32 bits) each. Each subsegment has an associated present (P) flag
to indicate whether or not the subsegment contains valid data.
The cache is loaded only when an instruction requested by the execution section of the SMJ34020A is not
already contained within the cache. A least-recently-used (LRU) algorithm determines which of the four
segments of the cache is overwritten with new data. For this purpose, an internal four-by-two LRU stack keeps
track of cache usage. Although the cache is loaded so as to always fill a subsegment completely, not all eight
subsegments within a segment are necessarily filled (this is dependent upon the instruction stream).
status register
The status register (ST) is a special purpose 32-bit register dedicated to status codes set by the results of implicit
and explicit compare operations and parameters used to specify the length and behavior of fields 0 and 1. During
an interrupt, when the IX bit in the ST is placed on the stack, it indicates that execution of an interruptable
instruction (PIXBLT, FILL or LINE) was halted to service the interrupt. The single-step bit causes a trap to the
single-step vector (located at address FFFF FBE0h) after the execution of one instruction when the bit is set
high. Normal program execution occurs when the bit is set low.
fields, bytes, words, long words, pixels and pixel arrays
The SMJ34020A outputs a 28-bit address on LAD4 – LAD31 that is valid at the falling edge of ALTCH. The most
significant 27 bits (LAD5 – LAD31) define a 32-bit-long word of physical memory; logically, however, the
SMJ34020A views memory data as fields addressable at the bit level. The least significant bit of the 28-bit
address (LAD4) is used to select the odd or even word when accessing 16-bit memories (indicated by SIZE16
asserted low). Primitive data types supported by the SMJ34020A include bytes, words, long words, pixels, two
independent fields of from 1 to 32 bits, and user-defined pixel arrays.
Words and long words, respectively, refer to 16- and 32-bit values that are aligned on 32-bit boundaries.
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