SMJ34020A Datasheet, PDF (85/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
multiprocessor-interface timing: high-impedance signals (see Note 4 and Figure 45)
NO.
84 td(CK1H-SFV) Delay time, SF valid after LCLK1 no longer low
86
td(CK2L-SFZ)
Delay time, SF in the high-impedance state after
LCLK2 no longer high
109
td(CK2L-ADZ)
Delay time, LAD and RCA in the high-impedance
state after LCLK2 no longer high
110
td(CK1H-ADV)
Delay time, LAD and RCA valid after LCLK1 no longer
low
Delay time, ALTCH, RAS, CAS, WE, TR / QE, HOE,
111 td(CK1H-CTZ) and HDST in the high-impedance state after LCLK1
no longer low
Delay time, ALTCH, RAS, CAS, WE, TR / QE, HOE,
112 td(CK2L-CTH) and HDST in the high-impedance state after LCLK2
no longer high
113
td(CK1H-DIZ)
Delay time, DDIN in the high-impedance state after
LCLK1 no longer low
114 td(CK2L-DIL) Delay time, DDIN low after LCLK2 no longer high
115
td(CK2L-DOZ)
Delay time, DDOUT in the high-impedance state after
LCLK2 no longer high
116 td(CK2L-DOH) Delay time, DDOUT high after LCLK2 no longer high
† _{These values are derived from characterization data and are not tested.}
NOTE 4: s = tQ if using the clock stretch;
s = 0 otherwise
’34020A-32
MIN
MAX
tQ+ 22
tQ+ 22+ s ^†
tQ+ 22+ s ^†
tQ+ 22
tQ+15 ^†
tQ + 15+ s
tQ + 15 ^†
tQ + 15 + s
tQ+15 + s^†
tQ + 15+ s
’34020A-40
MIN
MAX
tQ + 20
tQ + 20 + s^†
tQ+ 20 + s^†
tQ + 20
tQ +13.5†
tQ + 13.5 + s
tQ + 13.5 ^†
tQ + 13.5+ s
tQ +13.5 + s^†
tQ + 13.5 + s
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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