SMJ34020A Datasheet, PDF (35/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
cycle timing examples (continued)
The clock stretch is generated by the VLCOL instruction and is indicated by CAS, WE, TR / QE, and SF high
at the falling edge of RAS and SF high at the falling edge of CAS (Figure 10). The data in the COLOR1 register
is output on LAD to be written to a special register on the VRAM that is used in subsequent cycles requiring a
color latch. During the address portion of the cycle, the status on LAD0 – LAD3 indicates a color-mask load is
being performed (status code = 0111). Although CAMD, PGMD, and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1
GI
LAD
Zero Address
Color Register Data
CAMD
RCA
All-Zero Address
ALTCH
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 20.}
Figure 10. Load-Color-Latch-Cycle Timing
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