SMJ34020A Datasheet, PDF (27/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
cycle timing examples (continued)
Standard Memory Write Cycle
Page-Mode Write
Address Subcycle
Data Transfer
Subcycle
Data Transfer
Subcycle
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLCK1
LCLCK2
GI
LAD
Address
Data Out 1
Data Out 2
CAMD
RCA
ALTCH
Row
1st Column
2nd Column
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
(see Note A)
PGMD
(see Note A)
SIZE16
(see Note A)
BUSFLT
(see Note A)
R0
R1
† _{See clock stretch, page 20.}
NOTE A: LRDY, PGMD, SIZE16, and BUSFLT are not sampled on subsequent page-mode cycle
accesses to 32-bit-wide memory space.
Figure 4. Local-Memory Write-Cycle Timing (With Page Mode)
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