SMJ34020A Datasheet, PDF (21/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
clock stretch (continued)
When clock-stretch mode is enabled, the fourth machine quarter cycle can be stretched to twice its original
length. This stretching takes place only when the SMJ34020A attempts certain types of memory cycles.
Normal Sequence
Possible New Sequence
Q1 Q2 Q3 Q4
Normal Cycle
Q1 Q2 Q3 Q4
Normal Cycle
Q1 Q2 Q3 Q4a Q4b Q1 Q2 Q3 Q4
Stretched Cycle
Normal Cycle
The stretch is achieved by holding the internal SMJ34020A clocks in the Q4 state for an extra quarter cycle so
all of the device outputs remain unchanged during Q4a and Q4b. The SMJ34020A stretches only certain
machine cycles so that the execution of code is not slowed unnecessarily.
enabling clock stretch
Clock-stretch mode is enabled and disabled using a bit in the CONFIG register memory mapped to location
C00001A0h, see Figure 1.
31
76543210
C
S
E
Loaded at Reset from Reset Vector
Protected Byte
CONFIG register
CSE = 0: Disable stretch mode (normal operation)
CSE = 1: Enable stretch mode
Bit 4 of the CONFIG register is the clock-stretch-enable mode bit. A zero in this bit disables stretch mode and
a one in this bit enables stretch mode. The bit is cleared during reset; that is, stretch mode is disabled by default.
When stretch mode is enabled, the following machine cycles are stretched:
D All address cycles of all memory-access sequences
D Read data cycles in read-modify-write sequences
Notes:
a) The host default cycle shown in the TMS34020 User’s Guide is not stretched because it is not a true
address cycle; that is, RAS, etc., do not go low.
b) The CPU default cycle, which is similar to the host default cycle in that RAS, etc., do not go low, is
also not stretched.
c) Clock-stretch mode disregards the page-mode input so that read data cycles in nonpage-mode
read-modify-write sequences are stretched even though there are no timing constraints that require
a stretch.
d) All other memory subcycles are not stretched, even if the SMJ34020A is running with the CSE bit
set to 1.
The advantage of this implementation of clock-stretch mode is that the SMJ34020A can execute code at
maximum speed, slowing down only during certain parts of memory access sequences.
It is important to remember that a stretched cycle is 25% longer than a normal cycle and that the SMJ34020A
(with the exception of the video logic, which is clocked independently by VCLK) effectively slows down during
such a stretched cycle.
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