SMJ34020A Datasheet, PDF (33/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
cycle timing examples (continued)
LCLCK1
Address Subcycle
Data Transfer
Subcycle
Data Transfer
Subcycle
Q4 Q1 Q2 Q3 _Q4^† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLCK2
GI
LAD0 – LAD15
Low Address
Data Low
Data High
LAD16 – LAD31
High Address
Data High
Data Low
CAMD
RCA
Row
Column (S=0)
Column (S=1)
ALTCH
RAS
CAS0
CAS1
CAS2
CAS3
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 20.}
Figure 8. Dynamic Bus Sizing, Write-Cycle Timing
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