SMJ34020A Datasheet, PDF (82/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
The refresh pseudo-address present on LAD0 – LAD31 is the output from the 16-bit refresh address
register([ I O] register located at C000 01F0h) on LAD16 – LAD31. LAD0 – LAD3 have the refresh status code
(status code = 0011), and LAD4 – LAD15 are held low.
CBR refresh: RAS and CAS0–CAS3 (see Note 4 and Figure 42)
NO.
Delay time, RAS low after LCLK1 no
76
td(CK1L-REL) _{longer high}
77
td(CK1L-REH)
Delay time, RAS high after LCLK1 no
longer high
78
td(CK1H-CEL)
Delay time, CAS low after LCLK1 no
longer low
79
td(CK1L-CEH)
Delay time, CAS high after LCLK1 no
longer high
102 td(REL-CEH)
Delay time, RAS low to CAS no longer
low
103 td(CEL-REL)
Delay time, CAS low to RAS no longer
high
104 td(REH-CEL)
Delay time, RAS high to CAS no longer
high
NOTE 4: s = tQ if using the clock stretch;
s = 0 otherwise
’34020A-32
MIN
MAX
tQ + 12 + s
tQ + 12
tQ + 12
tQ + 12
4tQ – 12 + s
2tQ – 15
2tQ – 15 + s
’34020A-40
MIN
MAX
tQ + 10 + s
tQ + 10
tQ + 10
tQ + 10
4tQ – 4 + s
2tQ – 13.5
2tQ – 13.5 + s
UNIT
ns
ns
ns
ns
ns
ns
ns
82
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