SMJ34020A Datasheet, PDF (20/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
coprocessor interface
Support for coprocessors is provided through special instructions and bus cycles that allow communication with
the coprocessor. A coprocessor can be register based, depending on the SMJ34020A to do all address
calculations, or it can operate as its own bus controller, using the multiprocessor arbitration scheme. Five basic
cycles are provided for direct communication and control of coprocessors:
D SMJ34020A to coprocessor
D Coprocessor to SMJ34020A
D Move memory to coprocessor
D Move coprocessor to memory
D Coprocessor internal command
The first four of these cycles provide for command of the coprocessor in addition to the movement of parameters
to and from the coprocessor. In this manner, parameters can be sent to the coprocessor and operated upon
without an explicit coprocessor command cycle.
instruction set
The SMJ34020A instruction set can be divided into five categories:
D Graphics instructions
D Coprocessor instructions
D Move instructions
D General-purpose instructions
D Program control and context switching
Specialized graphics instructions manipulate pixel data that is accessed using memory addresses or
XY coordinates. These instructions include graphics operations, such as array and raster operations, pixel
processing, windowing, plane masking, pixel masking, and transparency. Coprocessor instructions allow for the
control and data flow to and from coprocessors that reside in the system. Move instructions comprehend the
bit-addressing and field operations, which manipulate fields of data using linear addressing for transfer to and
from memory and the register file. General-purpose instructions provide a complete set of arithmetic and
Boolean operations on the register file as well as general program control and data processing. Program control
and context switching instructions allow the user to control flow and to save and restore information using
instructions with both register-direct and absolute operands.
clock stretch
The SMJ34020A supports a clock stretching mechanism, that is described below.
With advances in semiconductor manufacturing, newer versions of the SMJ34020A can be made, each
supporting a higher CLKIN frequency. The increase in CLKIN frequency means that the SMJ34020A machine
cycles execute more quickly, with a consequent increase in code execution speed. However, there comes a
point when, as the machine cycle time becomes shorter, the local-memory control signals begin to violate DRAM
and VRAM timing parameters for certain types of memory access.
The clock-stretch mechanism allows the SMJ34020A to slow down and execute those critical local-memory
cycles while still benefiting from the accelerated processing allowed by higher CLKIN frequencies during
noncritical memory access cycles.
Exact timing issues vary from system to system, reflecting differences in bus buffering, etc., but, broadly
speaking, the clock-stretch mechanism allows the system designer to interface to slower memory devices than
the designer could use if no stretch mechanism was available.
A normal, unstretched machine cycle consists of four quarter cycles, Q1, Q2, Q3, and Q4. A stretched cycle
consists of five quarter cycles, Q1, Q2, Q3, Q4a, and Q4b.
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