SMJ34020A Datasheet, PDF (24/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
cycle timing examples (continued)
LCLK1
LCLK2
GI
Standard Memory Read Cycle
Page-Mode Read
Address Subcycle
Data Transfer
Subcycle
Data Transfer
Subcycle
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LAD (SMJ34020A)
(see Note A)
LAD (Memory)
(see Note A)
CAMD
Address
Data
Data
RCA
Row
1st Column
2nd Column
ALTCH
RAS
CAS
WE
TR/ QE
SF
DDIN
DDOUT
LRDY
(see Note B)
PGMD
(see Note B)
SIZE16
(see Note B)
BUSFLT
(see Note B)
R0
R1
† _{See clock stretch, page 20.}
NOTES: A. LAD (SMJ34020A): Output to LAD by the SMJ34020A
LAD (memory): Output to LAD by the memory.
B. LRDY, PGMD, SIZE16, and BUSFLT are not sampled on subsequent page-mode cycle accesses to
32-bit-wide memory space.
Figure 2. Local-Memory Read-Cycle Timing (with page mode)
24
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443