SMJ34020A Datasheet, PDF (10/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
fields, bytes, words, long words, pixels and pixel arrays (continued)
The two independent fields are referenced as field 0 and field 1. The attributes of these fields (field size and sign
extension within a register) are defined in the status register as FS0, FE0, FS1, and FE1. Fields 0 and 1 are
specified independently to be signed or unsigned and from 1 to 32 bits in length. Bytes are special 8-bit cases
of the field data type, while pixels are 1, 2, 4, 8, 16, or 32 bits in length. In general, fields (including bytes) can
start and terminate on arbitrary bit boundaries; however, pixels must pack evenly into 32-bit-long words.
pixel operations
Pixel arrays are two-dimensional data types of user-defined width, length, pixel depth (number of bits per pixel),
and pitch (distance between rows). A pixel or pixel array can be accessed by means of either its memory address
or its XY coordinates. Transfers of individual pixels or pixel blocks are influenced by the pixel processing,
transparency, window checking, plane masking, pixel masking, or corner adjustment operations selected. For
further information, see the TMS32020 User’s Guide, literature number SPVU019.
transparency
Transparency is a mechanism that allows the surrounding pixels in an array to be specified as invisible. This
is useful for ensuring that only the object and not the rectangle surrounding it are written to the display. The
SMJ34020A provides four transparency modes:
D No transparency
D Transparency on result equal zero
D Transparency on source equal COLOR0
D Transparency on destination equal COLOR0
D Refer to the TMS34020 User’s Guide for more information.
I/O registers
The SMJ34020A contains an on-chip block of sixty-four 16-bit locations (mapped into the SMJ34020A’s
memory address space) that are used for I/O control registers. Eight of these are used by the host interface logic
and are not available to the user. Forty-seven I/O registers control parameters necessary to configure the
operation and report status of the following interfaces:
D Host interface
D Local memory
D Video timing
D Screen refresh
D External interrupts
D Internal interrupts
host interface registers
The host interface registers (HSTDATA, HSTADRL, HSTADRH, HSTCTLL, and HSTCTLH) are provided to
facilitate communications between the SMJ34020A and a host processor and maintain compatibility with the
SMJ34010. The registers are mapped into five of the I/O locations accessible to the SMJ34020A.
Two of these registers (HSTCTLL and HSTCTLH) are used to provide control by the host. This control consists
of the passing of interrupt requests, flushing the instruction cache, halting the SMJ34020A, transmitting a
non-maskable interrupt request to the SMJ34020A, enabling emulation interrupts, and setting host access
modes and configurations.
The other three registers are simple read/write registers to allow the SMJ34020A software to leave addresses
for the host at a known location and allow compatibility with some SMJ34010 software.
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