SMJ34020A Datasheet, PDF (73/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
host-interface-cycle timing responses (random read cycle) (see Note 4 and Figure 37)
NO.
26 tw(RDH)
Pulse duration, HREAD high
33
tsu(RDL-CK2L)
Setup time, HCS low or HREAD low to LCLK2 no
longer high
39
td(CK1H-RYH)
Delay time, LCLK1 going high to HRDY high (end of
read cycle)
40 td(RDH-RYL) Delay time, HREAD or HCS high to HRDY low
41 td(CK2L-STL) Delay time, LCLK2 no longer high to HDST low
42 td(CK1L-STH) Delay time, LCLK1 no longer high to HDST high
43 tsu(STL-RYH) Setup time, HDST low to HRDY no longer low
44 td(RYH-STH) Delay time, HRDY no longer low to HDST high
† _{Setup time to ensure recognition of input on this clock edge.}
NOTE 4: s = tQ if using the clock stretch;
s = 0 otherwise
’34020A -30
MIN MAX
28
30†
tQ + 20
s+
tQ–15
20
tQ + 15
tQ + 15
2tQ + 15
’34020A-40
MIN
MAX
25
UNIT
ns
25†
ns
tQ+18 ns
18 ns
tQ + 13.5+s ns
tQ –13.5 ns
2tQ + 13.5 ns
2tQ + 13.5 ns
.
Q4 Q1 Q2 Q3 Q4‡ Q1 Q2 Q3 Q4
LCLK1
LCLK2
33
HCS/HREAD
39
33
26
HRDY
40
41
HDST
‡ _{See clock stretch, page 20.}
42
44
43
Figure 37. Host-Interface-Cycle Timing Responses (Random Read Cycle)
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