SMJ34020A Datasheet, PDF (63/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
DC electrical characteristics over recommended range of supply voltage (see Note 3)
PARAMETER
TEST CONDITIONS MIN TYP^† MAX
UNIT
BUSFLT, LRDY, VCLK,
PGMD, SIZE16, CSYNC,
VSYNC, HSYNC
GB PKG
HT PKG
2.2
VCC + 0.3
2.3
VCC + 0.3
VIH
VIL
VOH
VOL
High-level input
voltage
HWRITE, HREAD
HA5 – HA31, HCS,
HBS0 – HBS3
GB PKG
HT PKG
GB PKG
HT PKG
CLKIN only
All other inputs
Low-level input voltage, HT only: HCS VIL = – 0.3 min, 0.7 V max
High-level output voltage
Low-level output
voltage
GB PKG
DDIN, HINT, HRDY, R0, R1,
EMU3
HYSNC, VSYNC
HT PKG
VCC = MIN,
IOH = MAX
VCC = MAX,
IOL = MIN
2
2.3
2
2.3
3
2
– 0.3
2.6
VCC + 0.3
VCC + 0.3
V
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
0.8
V
V
0.60
0.8
V
0.8
All other outputs
IO
Output current, leakage (high impedance)
II
Input current (All inputs except EMU0 – EMU2,
HREAD, HWRITE‡)
GB PKG
HT PKG
GB PKG
HT PKG
VCC = MAX,
VO = 2.8 V
VCC = MAX,
VO = 0.6 V
VI = VSS to VCC
0.6
20
20
µA
– 20
– 20
±20
µA
ICC Supply current
’34020A-32
’34020A-40
VCC = MAX,
Freq = MAX
265
mA
280
Ci
Input capacitance
10
18
pF
Co Output capacitance
18
25
pF
† _{All typical values are at VCC = 5 V, TA = 25° C.}
‡ _{EMU0 – EMU2 are not connected in a typical configuration. Nominal pullup current for EMU0 – EMU2 and HREAD, HWRITE is 600 µA.}
NOTE 3: HDST and HOE (output terminals) have internal pullup resistors that allow high logic levels to be maintained when the SMJ34020A is
not actually driving these pins.
signal transition levels
2V
(see Note A)
0.8 V
NOTE A: 2.2 V for BUSFLT, VCLK, LRDY, PGMD, SIZE16. 3V for CLKIN.
Figure 30. TTL-Level Inputs
For high-to-low and low-to-high transitions, the level at which the input timing is measured is 1.5 V.
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