SMJ34020A Datasheet, PDF (7/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
PIN
NAME
VCC‡
VSS‡
EMU0 – EMU 2
EMU3
GI
R1, R0
Pin Functions (Continued)
I/O ^†
I
I
I
O
I
O
DESCRIPTION
POWER
Nominal 5-V power supply inputs. Five pins on QFP; Nine pins on PGA.
Electrical ground inputs. Nine pins on QFP; 17 pins on PGA.
EMULATION CONTROL
Emulation pins 0 – 2
Emulation pin 3
MULTIPROCESSOR INTERFACE
Bus grant input. External bus arbitration logic drives GI low to enable the SMJ34020A to gain access to the
local-memory bus. The SMJ34020A must release the bus if GI is high so that another device can access the bus.
Bus request and control. R1 and R0 indicate a request for use of the bus in a multiprocessor system; they are
decoded as shown below:
R1 R0
LL
LH
HL
HH
Bus Request Type
High-priority bus request
Bus-cycle termination
Low-priority bus request
No bus request pending
A high-priority bus request provides for VRAM serial-data-register transfer cycles (midline or blanked), DRAM
refresh (when 12 or more refresh cycles are pending), or a host-initiated access. The external arbitration logic
should grant the request as soon as possible by asserting GI low.
A low-priority bus request is used to provide for CPU-requested access and DRAM refresh (when less than
12 refresh cycles are pending).
Bus-cycle termination status is provided so that the arbitration logic can determine that the device currently
accessing the bus is completing an access, and other devices can compete for the next bus cycle. A
no-bus-request-pending status is output when the currently active device does not require the bus on subsequent
cycles.
VIDEO INTERFACE
CBLNK / VBLNK
O Composite blanking / vertical blanking. CBLNK / VBLNK can be programmed to select one of two blanking
functions:
Composite blanking for blanking the display during both horizontal and vertical retrace periods in
composite-sync-video mode
Vertical blanking for blanking the display during vertical retrace in separate-sync-video mode.
Immediately following reset, CBLNK / VBLNK is configured as a CBLNK output.
CSYNC / HBLNK I/O Composite sync / horizontal blanking. CSYNC / HBLNK can be programmed to select one of two functions:
Composite sync (either input or output as set by a control bit in the DPYCTL register) in
composite-sync-video mode:
As an input, extracts HSYNC and VSYNC from externally generated horizontal sync pulses
As an output, CSYNC / HBLNK generates active-low composite-sync pulses from either externally
generated HSYNC and VSYNC signals or signals generated by the SMJ34020A’s on-chip video timers
Horizontal blank (output only) for blanking the display during horizontal retrace in separate-sync-video mode.
Immediately following reset, CSYNC / HBLNK is configured as a CSYNC input.
HSYNC
I/O Horizontal sync. HSYNC is the horizontal sync signal that controls external video circuitry. HSYNC can be
programmed to be either an input or an output by modifying a control bit in the DPYCTL register.
As an output, HSYNC is the active-low horizontal-sync signal generated by the SMJ34020A’s on-chip video
timers.
As an input, HSYNC synchronizes the SMJ34020A video-control registers to externally generated
horizontal-sync pulses. The actual synchronization can be programmed to begin at any VCLK cycle; this
allows for any external pipelining of signals.
Immediately following reset, HSYNC is configured as an input.
† _{I = input, O = output}
‡ _{For proper SMJ34020A operation, all VCC and VSS pins must be connected externally.}
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