SMJ34020A Datasheet, PDF (12/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
memory controller/local-memory interface
The memory controller manages the SMJ34020A’s interface to the local memory and automatically performs
the bit alignment and masking necessary to access data located at arbitrary bit boundaries within memory. The
memory controller operates autonomously with respect to the CPU. It has a write queue one field (1 to 32 bits)
deep that permits it to complete those memory cycles necessary to insert a field into memory without delaying
the execution of subsequent instructions. Only when a second memory operation is required before completion
of the first operation is the SMJ34020A forced to defer execution of the subsequent instruction.
The SMJ34020A directly interfaces to standard DRAMs and in particular, to standard video RAMs (VRAMs)
such as the SMJ44C25x multiport VRAMs. The SMJ34020A memory interface consists of the local
address/data bus (LAD), the DRAM row/column address (RCA) bus, and associated control signals. The
currently selected word address (28 bits) and status (4 bits) are multiplexed with data on LAD. The RCA bus
allows direct connection to address/address multiplexed DRAMs from 64K to 16M. Refresh for DRAMs is
supported by CAS-before-RAS (CBR) refresh cycles.
ADDRESS
BIT 232 –1
(Last Bit in Memory)
FFFFFFF0h
FFFFFBC0h
FFFFFBB0h
FFFFE000h
FFFFDFF0h
FFFF0000h
FFEFFFF0h
C0004000h
C0003FF0h
68 Words
444 Words
65024 Words
226 – 66560 Words
(67 042 304 Words)
512 Words
Interrupt Vectors and
Extended Trap Vectors
Reserved for Interrupt Vectors
and Extended Trap Vectors
General Use and
Extended Trap Vectors
General Use
Reserved for System I/O
C0002000h
C0001FF0h
448 Words
Reserved for I/O Registers
C0000400h
C00003F0h
64 Words
I/O Registers
C0000000h
BFFFFFF0h
00100000h
000FFFF0h
00000000h
(3 × 226) – 64K
(201 261 056 Words)
64K Words
16
General Use
General Use and Extended
Trap Vectors
Bit 0
(First Bit in Memory)
Figure 1. Memory Map
12
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