SMJ34020A Datasheet, PDF (17/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
local memory and DRAM/VRAM interface (continued)
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
Similarly, for each of the other VRAM modes, direct connection is provided for other DRAM modes requiring
larger matrices than the configuration mode. The following table gives examples of the connections using this
feature.
RCA
64K†
CONNECTIONS TO RCA FOR CAMD = 1
256K†
12
1M × 32
4M × 32
11
1M × 16
1M × 32
4M × 32
10
256K × 32
1M × 32
1M × NN
4M × 32
9
256K × NN
1M × NN
1M × NN
4M × 32
8
256K × NN
1M × NN
1M × NN
4M × 32
7
256K × NN
1M × NN
1M × NN
4M × 32
6
256K × NN
1M × NN
1M × NN
4M × 32
5
256K × NN
1M × NN
1M × NN
4M × 32
4
256K × NN
1M × NN
1M × NN
4M × 32
3
256K × NN
1M × NN
1M × NN
4M × 32
2
256K × NN
1M × NN
1M × NN
4M × 32
1
256K × 16
1M × 16
1M × 16
0
† _{NN is used for either 16-bit (× 16) or 32-bit (× 32) memory connections.}
1M†
4M × 32
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × 16
4M
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
status codes
Status codes are output on LAD0 – LAD3 at the time of the falling edge of ALTCH and can be used to determine
the type of cycle that is being initiated. The following table lists the codes and their respective meanings.
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
STATUS
Coprocessor code
Emulator operation
Host cycle
DRAM refresh
Video-generated DRAM serial register transfer
CPU-generated VRAM serial register transfer
Write mask load
Color latch load
Data access
Cache fill
Instruction fetch
Interrupt vector fetch
Bus locked operation
Pixel operation
Block write
– RESERVED –
TYPE
OTHER
(00XX)
VRAM
(01XX)
CPU
(1XXX)
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