SMJ34020A Datasheet, PDF (77/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
local-bus timing: bus control inputs (see Note 4 and Figure 41)
’34020A-32
’34020A-40
NO.
UNIT
MIN
MAX
MIN
MAX
57
td(CK2H-ALL)
Delay time, ALTCH low after LCLK2 no
longer low
tQ + 15
tQ + 13.5 ns
58
td(CK1L-ALH)
Delay time, ALTCH high after LCLK1 no
longer high
tQ + 15
tQ + 13.5 ns
Delay time, LAD0 – LAD31 address valid
59
td(CK1H-LAV) _{after LCLK1 no longer low}
tQ + 22
tQ + 20 ns
60
th(LAV-CK2L)
Hold time, LAD0 – LAD31 address valid after
LCLK2 low
tQ – 15 + s
tQ – 12 + s
ns
Delay time, LAD0 – LAD31 driven after
61
td(CT-LAD)
earlier of DDIN no longer high or CAS no tQ – 5 + s ^†
tQ – 5 + s ^†
ns
longer low or TR/QE no longer low
Hold time, LAD0 – LAD31 read data valid
62
th(_LAV-CTV)
after earlier of DDIN low or RAS, CAS, or
3.5
TR/QE low
3.5
ns
Delay time, LAD0 – LAD31 data valid after
63
td(CK2L-LAV) _{LCLK2 no longer high (write)}
tQ + 22 + s
tQ + 20 + s ns
64
th(CK2L-LAV)
Hold time, LAD0 – LAD31 data valid after
LCLK2 low (write)
tQ – 15
tQ – 13.5
ns
65
td(CK1H-RCV)
Delay time, RCA0 – RCA12 row address
valid after LCLK1 no longer low
tQ + 22
tQ + 22 ns
66
td(CK2L-RCV)
Delay time, LAD0 – LAD31 column address
valid after LCLK2 no longer high
tQ + 22 + s
tQ + 20+ s ns
67
th(RCV-CK2L)
Hold time, RCA0-RCA12 address valid after
LCLK2 low
tQ – 15
tQ – 13.5
ns
68
td(CK1H-DIH)
Delay time, DDIN high after LCLK1 no longer
low
tQ + 15
tQ + 13.5 ns
69
td(CK1L-DIL)
Delay time, DDIN low after LCLK1 no longer
high
tQ + 15
tQ + 13.5 ns
70
td(CK1H-DOL)
Delay time, DDOUT low after LCLK1 no
longer low
tQ + 15
tQ + 13.5 ns
71
td(CK1L-DOH)
Delay time, DDOUT high after LCLK1 no
longer high
tQ + 15
tQ + 13.5 ns
Delay time, DDOUT low after LCLK2 no
72
td(CK2L-DOL) _{longer high}
tQ + 15 + s
tQ + 13.5 + s ns
73
tsu(LAV-ALL)
Setup time, LAD0 – LAD31 data valid before
ALTCH no longer high
tQ – 16
tQ – 13.5
ns
74
ten(DAV-DIH)
Enable time, data valid after DDIN high
(see Note 7)
2tQ – 20
2tQ – 17 ns
75
tdis(DAV-DIL)
Disable time, data in the high-impedance
state after DDIN low (see Note 7)
tQ – 12 + s ^†
tQ – 10 + s^† ns
† _{These values are derived from characterization data and are not tested.}
NOTES: 4. s = tQ if using the clock stretch;
s = 0 otherwise
7. DDIN is used to control LAD bus buffers between the SMJ34020A and local memory. Parameter 74 references the time for these
data buffers to go from the high-impedance state to an active level. Parameter 75 references the time for the buffers to go from an
active level to the high-impedance state.
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