SMJ34020A Datasheet, PDF (29/92 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011B – APRIL 1991 – REVISED AUGUST 1995
cycle timing examples (continued)
The refresh pseudo-address output to RCA0 – RCA12 and LAD0 – LAD31 comes from the 16-bit refresh
address register (I/O register C000 01F0h) that is incremented after each refresh cycle (Figure 6). The 16 bits
of address are placed on LAD16 – LAD31; all other LAD bus lines are zero. The logical addresses on
RCA0– RCA12 corresponding to LAD16 – LAD31 also output the address from the refresh-address register.
Although PGMD and SIZE16 are ignored during a refresh cycle, they should be held at valid levels. LRDY and
BUSFLT are not sampled until the start of the first Q2 cycle after RAS has gone low.
If a refresh cycle is aborted due to a high-priority bus request (assuming LRDY is low at Q2 after RAS low), a
bus fault, or an external retry, then the count of refreshes pending is not decremented and the same
pseudo-address is reissued when the refresh is restarted.
Refresh Status
CBR
Refresh End
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLCK1
LCLCK2
GI
LAD
Refresh Pseudo-Address
CAMD
RCA
Refresh Psuedo-Address
ALTCH
RAS
CAS
WE
TR/ QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 20.}
Figure 6. Refresh-Cycle Timing
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
29