SMJ320LC549 Datasheet, PDF (8/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Signal Descriptions (Continued)
TERMINAL
NAME
TYPE^†
DESCRIPTION
HOST-PORT INTERFACE SIGNALS
HD0–HD7
I/O/Z
Parallel bidirectional data bus. HD0–HD7 are placed in the high-impedance state when not outputting data. The
signals go into the high-impedance state when EMU1/OFF is low. These pins each have bus holders similar to
those on the address/data bus, but which are always enabled.
HCNTL0
HCNTL1
I
Control inputs
HBIL
I
Byte-identification input
HCS
I
Chip-select input
HDS1
HDS2
I
Data strobe inputs
HAS
I
Address strobe input
HR/W
I
Read/write input
HRDY
HINT
O/Z
Ready output. This signal goes into the high-impedance state when EMU1/OFF is low.
O/Z
Interrupt output. When the DSP is in reset, this signal is driven high. The signal goes into the high-impedance
state when EMU1/OFF is low.
HPIENA
HPI module select input. This signal must be tied to a logic 1 state to have HPI selected. If this input is left open
or connected to ground, the HPI module will not be selected, internal pullup for the HPI input pins are enabled,
I
and the HPI data bus has keepers set. This input is provided with an internal pull-down resistor which is active
only when RS is low. HPIENA is sampled when RS goes high and ignored until RS goes low again. Refer to the
Electrical Characteristics section for the input current requirements for this pin.
SUPPLY PINS
CVDD
DVDD
VSS
Supply
Supply
Supply
+VDD. CVDD is the dedicated power supply for the core CPU.
+VDD. DVDD is the dedicated power supply for I/O pins.
Ground. VSS is the dedicated power ground for the device.
IEEE1149.1 TEST PINS
TCK
IEEE standard 1149.1 test clock. Pin with internal pullup device. This is normally a free-running clock signal with
I
a 50% duty cycle. The changes on the test-access port (TAP) of input signals TMS and TDI are clocked into the
TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP
output signal (TDO) occur on the falling edge of TCK.
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
TDI
I
(instruction or data) on a rising edge of TCK.
TDO
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out
O/Z
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
I
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0
I/O/Z
Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF
condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined
as input/output by way of IEEE standard 1149.1 scan system.
† _{I = Input, O = Output, Z = High impedance}
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