SMJ320LC549 Datasheet, PDF (21/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
memory and parallel I/O interface timing (continued)
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
switching characteristics over recommended operating conditions for a parallel I/O port write
(IOSTRB = 0) [H = 0.5 t_c(CO)] (see Figure 8)^†
PARAMETER
td(CLKL-A)
Delay time, address valid from CLKOUT low^‡
td(CLKH-ISTRBL) Delay time, IOSTRB low from CLKOUT high
td(CLKH-D)IOW Delay time, write data valid from CLKOUT high
td(CLKH-ISTRBH) Delay time, IOSTRB high from CLKOUT high
td(CLKL-RWL)
td(CLKL-RWH)
th(A)IOW
Delay time, R/W low from CLKOUT low
Delay time, R/W high from CLKOUT low
Hold time, address valid from CLKOUT low^‡
th(D)IOW
Hold time, write data after IOSTRB high
tsu(D)IOSTRBH Setup time, write data before IOSTRB high
tsu(A)IOSTRBL Setup time, address valid before IOSTRB low
*Not production tested.
† _{See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.}
‡ _{Address and IS timings are included in timings referenced as address.}
549-60
MIN MAX
–1.5*
7
–0.5*
6
H–5* H+8.5
–1*
6
–0.5*
6
–1*
6
–1.5*
7*
H–5* H+5*
H–5* H+2*
H–5* H+5*
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
td(CLKL-A)
A[15:0]
td(CLKH-D)IOW
tsu(A)IOSTRBL
D[15:0]
IOSTRB
R/W
td(CLKH-ISTRBL)
td(CLKH-ISTRBH)
td(CLKL-RWL)
th(A)IOW
th(D)IOW
tsu(D)IOSTRBH
td(CLKL-RWH)
IS
Figure 8. Parallel I/O Port Write (IOSTRB = 0)
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