SMJ320LC549 Datasheet, PDF (13/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
internal oscillator with external crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent –
see PLL section) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half the crystal’s oscillation frequency following reset. After reset, the clock mode of the devices
with the software PLL can also be changed to divide-by-four. Since the internal oscillator can be used as a clock
source to the PLL, the crystal oscillation frequency can be multiplied to generate the CPU clock if desired.
The crystal should be in fundamental mode operation and parallel resonant with an effective series resistance
of 30ohms and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and
two load capacitors, is shown in Figure 2. The load capacitors, C₁ and C₂, should be chosen such that the
equation below is satisfied. C_L in the equation is the load specified for the crystal.
C_L
+
C₁C₂
(C₁ ) C₂)
recommended operating conditions (see Figure 2)
fx
Input clock frequency
*Not production tested.
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.}
‡ _{It is recommended that the PLL clocking option be used for maximum frequency operation.}
549-60
MIN MAX
10^†* 20^‡*
UNIT
MHz
X1
C1
X2/CLKIN
Crystal
C2
Figure 2. Internal Divide-by-Two Clock Option With External Crystal
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