SMJ320LC549 Datasheet, PDF (20/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port read
(IOSTRB = 0)^†‡ (see Figure 7)
PARAMETER
td(CLKL-A)
Delay time, address valid from CLKOUT low
td(CLKH-ISTRBL) Delay time, IOSTRB low from CLKOUT high
td(CLKH-ISTRBH) Delay time, IOSTRB high from CLKOUT high
th(A)IOR
Hold time, address after CLKOUT low
*Not production tested.
† _{Address and IS timings are included in timings referenced as address.}
‡ _{See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.}
549-60
MIN MAX
–1.5*
7
–0.5*
6
–1*
6
–1.5*
7*
UNIT
ns
ns
ns
ns
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 t_c(CO)]^†‡ (see Figure 7)
ta(A)IO
Access time, read data access from address valid
ta(ISTRBL)IO
Access time, read data access from IOSTRB low
tsu(D)IOR
Setup time, read data before CLKOUT high
th(D)IOR
Hold time, read data after CLKOUT high
th(ISTRBH-D)R Hold time, read data after IOSTRB high
*Not production tested.
† _{Address and IS timings are included in timings referenced as address.}
‡ _{See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.}
549-60
MIN MAX
3H–10*
2H–10*
5*
2*
0*
UNIT
ns
ns
ns
ns
ns
CLKOUT
A[15:0]
D[15:0]
IOSTRB
td(CLKL-A)
th(A)IOR
ta(A)IO
th(D)IOR
tsu(D)IOR
ta(ISTRBL)IO
td(CLKH-ISTRBL)
th(ISTRBH-D)R
td(CLKH-ISTRBH)
R/W
IS
Figure 7. Parallel I/O Port Read (IOSTRB = 0)
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