SMJ320LC549 Datasheet, PDF (28/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
HOLD and HOLDA timings
switching characteristics over recommended operating conditions for memory control signals
and HOLDA [H = 0.5 t_c(CO)] (see Figure 14)
PARAMETER
tdis(CLKL-A)
tdis(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-A)
ten(CLKL-RW)
ten(CLKL-S)
Disable time, CLKOUT low to address, PS, DS, IS high impedance
Disable time, CLKOUT low to R/W high impedance
Disable time, CLKOUT low to MSTRB, IOSTRB high impedance
Enable time, CLKOUT low to address, PS, DS, IS
Enable time, CLKOUT low to R/W enabled
Enable time, CLKOUT low to MSTRB, IOSTRB enabled
tv(HOLDA)
Valid time, HOLDA low after CLKOUT low
Valid time, HOLDA high after CLKOUT low
tw(HOLDA)
Pulse duration, HOLDA low duration
*Not production tested.
549-60
MIN MAX
5*
5*
5*
2H+5*
2H+5*
2H+5*
UNIT
ns
ns
ns
ns
ns
ns
0* 5*
ns
0* 5*
ns
2H–3*
ns
timing requirements for HOLD [H = 0.5 t_c(CO)] (see Figure 14)
tw(HOLD)
Pulse duration, HOLD low duration
tsu(HOLD)
Setup time, HOLD before CLKOUT low
*Not production tested.
549-60
MIN MAX
4H+10*
10*
UNIT
ns
ns
28
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