SMJ320LC549 Datasheet, PDF (43/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

host-port interface timing (continued)
SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
timing requirements [H = 0.5t_c(CO)] (see Note 5, Figure 29 through Figure 32)
549-60
UNIT
MIN MAX
tsu(HBV-DSL)
Setup time, HAD/HBIL valid before DS or HAS falling edge
10*
ns
th(DSL-HBV)
Hold time, HAD/HBIL valid after DS or HAS falling edge
5*
ns
tsu(HSL-DSL)
tw(DSL)
Setup time, HAS low before DS falling edge
Pulse duration, DS low
12*
ns
30*^†
ns
tw(DSH)
Pulse duration, DS high
10*
ns
Case 1: HOM access timings
(see Access Timings Without HRDY)
50*
tc(DSH-DSH)^†
Cycle time, DS rising edge to next DS
rising edge
Case 2a: SAM accesses and HOM active writes
ns
to DSPINT or HINT.
10H*
(see Access Timings With HRDY)
tsu(HDV-DSH)
td(DSH-HSL)^‡
Setup time, HD valid before DS rising edge
Delay time, DS high to next HAS low
12*
ns
10H*
ns
th(DSH _{– HDV)W} Hold time, HD valid after DS rising edge, write
3.5*
ns
*Not production tested.
† _{A host not using HRDY should meet the 10H requirement all the time unless a software handshake is used to change the access rate according}
to the HPI mode.
‡ _{Must only be met if HAS is going low when not accessing the HPI (as would be the case where multiple devices are being driven by one host).}
NOTE 5: SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
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