SMJ320LC549 Datasheet, PDF (14/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
divide-by-two/divide-by-four clock option – PLL disabled
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)] (see Figure 2 and
Figure 3, and the recommended operating conditions table)
PARAMETER
tc(CO)
Cycle time, CLKOUT
td(CIH-CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT^†
Rise time, CLKOUT^†
Pulse duration, CLKOUT low^†
Pulse duration, CLKOUT high^†
*Not production tested.
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.}
549-60
MIN TYP
2tc(CI)
3*
6
2
2
H–4* H–2
H–4* H–2
MAX
†
10*
H*
H*
UNIT
ns
ns
ns
ns
ns
ns
timing requirements (see Figure 3)
tc(CI) Cycle time, X2/CLKIN
tf(CI) Fall time, X2/CLKIN
tr(CI) Rise time, X2/CLKIN
tw(CIL) Pulse duration, X2/CLKIN low
tw(CIH) Pulse duration, X2/CLKIN high
*Not production tested.
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.}
‡ _{It is recommended that the PLL clocking option be used for maximum frequency operation.}
549-60
MIN MAX
20^‡
†
8*
8*
7*
†
7*
†
UNIT
ns
ns
ns
ns
ns
X2/CLKIN
tc(CI)
CLKOUT
tc(CO)
td(CIH-CO)
tw(CIH)
tw(CIL)
tf(CO)
tr(CI)
tf(CI)
tr(CO)
tw(COH)
tw(COL)
Figure 3. External Divide-by-Two Clock Timing
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