SMJ320LC549 Datasheet, PDF (15/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
multiply-by-N clock option – PLL enabled
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator
section.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)] (see Figure 2 and
Figure 4, and the recommended operating conditions table)
PARAMETER
tc(CO)
td(CIH-CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
tp
Cycle time, CLKOUT
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
*Not production tested.
† _{Tested with N = 3 only.}
MIN
16.7^†
549-60
TYP
tc(CI)/N
6
2
2
H–2
H–2
MAX
50*
UNIT
ns
ns
ns
ns
ns
ns
ms
timing requirements (see Figure 4)
tc(CI) Cycle time, X2/CLKIN
Integer PLL multiplier N (N = 1–15)
PLL multiplier N = x.5
PLL multiplier N = x.25, x.75
tf(CI) Fall time, X2/CLKIN
tr(CI) Rise time, X2/CLKIN
tw(CIL) Pulse duration, X2/CLKIN low
tw(CIH) Pulse duration, X2/CLKIN high
*Not production tested.
‡ _{Note that for all values of tc(CI), the minimum tc(CO) period must not be exceeded.}
549-60
MIN
20^‡*
20^‡*
MAX
200*
100*
20^‡* 50*
8*
8*
5*
5*
UNIT
ns
ns
ns
ns
ns
tw(CIH)
tc(CI)
tw(CIL)
tr(CI)
tf(CI)
X2/CLKIN
CLKOUT
td(CIH-CO)
tc(CO)
tp
Unstable
tw(COH)
tf(CO)
tw(COL)
tr(CO)
Figure 4. External Multiply-by-One Clock Timing
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