SMJ320LC549 Datasheet, PDF (12/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
electrical characteristics and operating conditions
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
VOH
VOL
IIZ
II
PARAMETER
High-level output voltage^‡
Low-level output voltage^‡
Input current in high ^A[22:0]
impedance
All other pins
TRST
Input current
(VI = VSS to VDD)
HPIENA
TMS, TCK, TDI, HPI^¶
D[15:0], HD[7:0]
X2/CLKIN
TEST CONDITIONS
VDD = 3.3±0.3 V, IOH = MAX
IOL = MAX
VDD = MAX^§
VDD = MAX, VI = VSS to VDD
With internal pulldown
With internal pulldown, RS = 0
RS = 1
With internal pullups
Bus holders enabled, VDD = MAX^§
Oscillator enabled
MIN TYP^†
2.4
–150
–10
–10
–20
–20
–400
–150
– 40
MAX
0.4
250
10
800
400
10
10
250
40
UNIT
V
V
µA
µA
IDDC
IDDP
IDD
All other input-only pins
Supply current, core CPU
Supply current, pins
Supply current,
standby
IDLE2
IDLE3
VDD = 3.3 V, fx = 40 MHz,# TC = 25°C
DVDD = 3.3 V, fx = 40 MHz,# TC = 25°C
PLL × 1 mode, 40 MHz input
Divide-by-two mode, CLKIN stopped
–10
28||
10.8k
2
15
10
mA
mA
mA
µA
Ci
Input capacitance
15 pF
Co
Output capacitance
15 pF
† _{All values are typical unless otherwise specified.}
‡ _{All input and output voltage levels except RS, INT0–INT3, NMI, X2/CLKIN, CLKMD1–CLKMD3 are LVTTL-compatible. Not applicable to X1}
which is an analog signal to a crystal oscillator.
§ _{VIL(MIN) ≤ VI ≤ VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX)}
¶ _{HPI input signals except for HPIENA.}
# _{Clock mode: PLL × 1 with external source}
|| _{This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being}
executed.
kThis value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320C54x Power Dissipation application report (literature number SPRA164).
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