SMJ320LC549 Datasheet, PDF (18/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a memory write
(MSTRB = 0) [H = 0.5 t_c(CO)]^†‡ (see Figure 6)
PARAMETER
td(CLKH-A)
td(CLKL-A)
Delay time, address valid from CLKOUT high^§
Delay time, address valid from CLKOUT low^¶
td(CLKL-MSL)
Delay time, MSTRB low from CLKOUT low
td(CLKL-D)W
td(CLKL-MSH)
Delay time, data valid from CLKOUT low
Delay time, MSTRB high from CLKOUT low
td(CLKH-RWL)
Delay time, R/W low from CLKOUT high
td(CLKH-RWH)
Delay time, R/W high from CLKOUT high
td(RWL-MSTRBL) Delay time, MSTRB low after R/W low
th(A)W
Hold time, address valid after CLKOUT high^§
th(D)MSH
Hold time, write data valid after MSTRB high
tw(SL)MS
Pulse duration, MSTRB low
tsu(A)W
Setup time, address valid before MSTRB low
tsu(D)MSH
Setup time, write data valid before MSTRB high
*Not production tested.
† _{Address, PS, and DS timings are all included in timings referenced as address.}
‡ _{See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.}
§ _{In the case of a memory write preceded by a memory write.}
¶ _{In the case of a memory write preceded by an I/O cycle.}
549-60
MIN MAX
–1.5*
6.5
–1.5*
7
–1.5*
6
0*
9
–1.5*
6
–1*
6
–1*
5.5
H – 4* H + 3*
–1.5*
7*
H–5* H+5*^¶
2H–5*
2H–5*
2H–10 2H+8*^§
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18
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