SMJ320LC549 Datasheet, PDF (16/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
memory and parallel I/O interface timing
switching characteristics over recommended operating conditions for a memory read
(MSTRB = 0)^†‡ (see Figure 5)
PARAMETER
td(CLKL-A)
td(CLKH-A)
Delay time, address valid from CLKOUT low^§
Delay time, address valid from CLKOUT high (transition)^¶
td(CLKL-MSL) Delay time, MSTRB low from CLKOUT low
td(CLKL-MSH)
th(CLKL-A)R
th(CLKH-A)R
Delay time, MSTRB high from CLKOUT low
Hold time, address valid after CLKOUT low^§
Hold time, address valid after CLKOUT high^¶
*Not production tested.
† _{Address, PS, and DS timings are all included in timings referenced as address.}
‡ _{See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.}
§ _{In the case of a memory read preceded by a memory read}
¶ _{In the case of a memory read preceded by a memory write}
549-60
MIN MAX
–1.5*
7
–1.5*
6.5
–1.5*
6
–1.5*
6
–1.5*
7
–1.5*
6.5
UNIT
ns
ns
ns
ns
ns
ns
timing requirements for a memory read (MSTRB = 0) [H = 0.5 t_c(CO)]^†‡ (see Figure 5)
549-60
MIN MAX
ta(A)M
ta(MSTRBL)
tsu(D)R
th(D)R
th(A-D)R
Access time, read data access from address valid
Access time, read data access from MSTRB low
Setup time, read data before CLKOUT low
Hold time, read data after CLKOUT low
Hold time, read data after address invalid
2H–10*
2H–10*
5
2
1*
th(D)MSTRBH Hold time, read data after MSTRB high
0*
*Not production tested.
† _{Address, PS, and DS timings are all included in timings referenced as address.}
‡ _{See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.}
UNIT
ns
ns
ns
ns
ns
ns
16
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