SMJ320LC549 Datasheet, PDF (2/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . 10
Parameter Measurement Information . . . . . . . . . . . . 11
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 12
Divide-by-Two/Divide-by-Four Clock Option . . . . . . 14
Multiply-by-N Clock Option . . . . . . . . . . . . . . . . . . . . . 15
Memory and Parallel I/O Interface Timing . . . . . . . . 16
I/O Timing Variation: SPICE Simulation . . . . . . . . . . 22
Ready Timing For Externally Generated
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . 28
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . 30
Instruction Acquisition (IAQ), Interrupt
Acknowledge (IACK), External Flag (XF),
and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . 33
Serial Port Receive Timing . . . . . . . . . . . . . . . . . . . . . 34
Serial Port Transmit Timing . . . . . . . . . . . . . . . . . . . . 35
Buffered Serial Port Receive Timing . . . . . . . . . . . . . 36
Buffered Serial Port Transmit Timing . . . . . . . . . . . . 38
Serial-Port Receive Timing in TDM Mode . . . . . . . . 40
Serial-Port Transmit Timing in TDM Mode . . . . . . . . 41
Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . . 42
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
description
The SMJ320LC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the 549) is based on an
advanced modified Harvard architecture that has one program memory bus and three data memory buses. The
processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific
hardware logic, on-chip memory, and additional on-chip peripherals. The 549 also utilizes a highly specialized
instruction set, which is the basis of its operational flexibility and speed.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions
with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be
transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the 549 includes
the control mechanisms to manage interrupts, repeated operations, and function calls.
This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the SMJ320LC549
DSP. For additional information, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital
Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional
overview and should be used in conjunction with this data sheet.
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