SMJ320LC549 Datasheet, PDF (6/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Signal Descriptions (Continued)
TERMINAL
NAME
TYPE^†
DESCRIPTION
INITIALIZATION, INTERRUPT AND RESET OPERATIONS (CONTINUED)
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
Reset input. RS causes the DSP to terminate execution and forces the program counter to 0FF80h. When RS
RS
I
is brought to a high level, execution begins at location 0FF80h of the program memory. RS affects various
registers and status bits.
MP/MC
Microprocessor/microcomputer mode-select pin. If active-low at reset (microcomputer mode), MP/MC causes
I
the internal program ROM to be mapped into the upper program memory space. In the microprocessor mode,
off-chip memory and its corresponding addresses (instead of internal program ROM) are accessed by the DSP.
MULTIPROCESSING SIGNALS
Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor executes
BIO
I
the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
XF
O/Z
by RSBX XF instruction or by loading the ST1 status register. XF is used for signaling other processors in
multiprocessor configurations or as a general-purpose output pin. XF goes into the high-impedance state when
OFF is low, and is set high at reset.
MEMORY CONTROL SIGNALS
DS
PS
IS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating
O/Z
to a particular external space. Active period corresponds to valid address information. Placed into a
high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state when EMU1/OFF is
low.
MSTRB
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data
O/Z
or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the high-impedance
state when OFF is low.
READY
Data-ready input. READY indicates that an external device is prepared for a bus transaction to be completed.
I
If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready-detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device and is normally
R/W
O/Z
high (in read mode), unless asserted low when the DSP performs a write operation. Placed in the high-impedance
state in hold mode, R/W also goes into the high-impedance state when EMU1/OFF is low.
IOSTRB
I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an I/O
O/Z
device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state when
EMU1/OFF is low.
HOLD
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the ’54x, these lines go into high-impedance state.
HOLDA
Hold acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that
O/Z
the address, data, and control lines are in a high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when EMU1/OFF is low.
MSC
Microstate complete signal. Goes low on CLKOUT falling at the start of the first software wait state. Remains low
O/Z
until one CLKOUT cycle before the last programmed software wait state. If connected to the READY line, MSC
forces one external wait state after the last internal wait state has been completed. MSC also goes into the
high-impedance state when EM1/OFF is low.
† _{I = Input, O = Output, Z = High impedance}
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