SMJ320LC549 Datasheet, PDF (38/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
buffered serial port transmit timing of external frames
switching characteristics over recommended operating conditions (see Figure 25)
PARAMETER
td(BDX)
Delay time, BDX valid after BCLKX rising
tdis(BDX)
Disable time, BDX after BCLKX rising
tdis(BDX)pcm Disable time, PCM mode, BDX after BCLKX rising
ten(BDX)pcm Enable time, PCM mode, BDX after BCLKX rising
th(BDX)
Hold time, BDX valid after BCLKX rising
*Not production tested.
549-60
MIN MAX
18*
4*
6*
6*
8*
2*
UNIT
ns
ns
ns
ns
ns
timing requirements (see Figure 25)
549-60
MIN
MAX
UNIT
tc(SCK)
Cycle time, serial port clock
20*
†
ns
tf(SCK)
Fall time, serial port clock
4*
ns
tr(SCK)
Rise time, serial port clock
4*
ns
tw(SCK)
th(BFSX)
Pulse duration, serial port clock low/high
Hold time, BFSX after BCLKX falling edge (see Notes 3 and 4)
6*
ns
6* tc(SCK)–6*^‡ ns
tsu(BFSX) Setup time, BFSX before BCLKX falling edge (see Notes 3 and 4)
6*
ns
*Not production tested.
† _{The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity.}
‡ _{If BFSX does not meet this specification, the first bit of the serial data is driven on BDX until BFSX goes low (sampled on falling edge of BCLKX).}
After falling edge of the BFSX, data is shifted out on the BDX pin.
NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined
depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.
4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.
BCLKX
tc(SCK)
tw(SCK)
tf(SCK)
BFSX
th(BFSX)
tsu(BFSX)
tw(SCK)
tr(SCK)
td(BDX)
th(BDX)
tdis(BDX)
BDX
1
2
8/10/12/16
Figure 25. Buffered Serial Port Transmit Timing of External Clocks and External Frames
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