SMJ320LC549 Datasheet, PDF (5/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
Signal Descriptions
TERMINAL
NAME
TYPE^†
DESCRIPTION
DATA SIGNALS
A22 (MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)
Parallel port address bus A22 (MSB) through A0 (LSB). The sixteen LSBs (A15–A0) are multiplexed to address
external data/program memory or I/O. A15–A0 are placed in the high-impedance state in the hold mode. A15–A0
also go into the high-impedance state when EMU1/OFF is low. The seven MSBs (A22 to A16) are used for
extended program memory addressing.
The address bus have a feature called bus holder that eliminates passive components and the power dissipation
associated with it. The bus holders keep the address bus at the previous logic level when the bus goes into a
high-impedance state. The bus holders on the address bus are always enabled.
O/Z
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
I/O/Z
Parallel port data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the core
CPU and external data/program memory or I/O devices. D15–D0 are placed in the high-impedance state when
not output or when RS or HOLD is asserted. D15–D0 also go into the high-impedance state when EMU1/OFF
is low.
The data bus has a feature called bus holder that eliminates passive components and the power dissipation
associated with it. The bus holders keep the data bus at the previous logic level when the bus goes into a
high-impedance state. These bus holders are enabled or disabled by the BH bit in the bank switching control
register (BSCR).
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK
Interrupt acknowledge signal. IACK indicates the receipt of an interrupt and that the program counter is fetching
O/Z
the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when
EMU1/OFF is low.
INT0
INT1
INT2
INT3
I
External user interrupt inputs. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the
interrupt mode bit. INT0 –INT3 can be polled and reset by the interrupt flag register.
† _{I = Input, O = Output, Z = High impedance}
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