SMJ320LC549 Datasheet, PDF (40/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
serial-port receive timing in TDM mode
timing requirements [H = 0.5t_c(CO)] (see Figure 27)
549-60
UNIT
MIN MAX
tc(SCK)
Cycle time, serial-port clock
16H*
† _ns
tf(SCK)
Fall time, serial-port clock
6* ns
tr(SCK)
Rise time, serial-port clock
6* ns
tw(SCK)
Pulse duration, serial-port clock low/high
8H*
ns
tsu(TD-TCH) Setup time, TDR/TADD before TCLK rising edge
10*
ns
th(TCH-TD) Hold time, TDR/TADD after TCLK rising edge
2*
ns
tsu(TF-TCH) Setup time, TFRM before TCLK rising edge‡
10*
ns
th(TCH-TF) Hold time, TFRM after TCLK rising edge‡
10*
ns
*Not production tested.
† _{The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching infinity.}
‡ _{TFRM timing and waveforms shown in Figure 27 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is}
illustrated in the transmit timing diagram in Figure 28.
tw(SCK)
tw(SCK)
tf(SCK)
TCLK
tc(SCK)
TDR
B0
tsu(TD-TCH)
th(TCH-TD)
tr(SCK)
B15
B14
B13
B12
B11 B2
B1
B0
tsu(TF-TCH)
TADD
A0
A1
A2
A3
A4 A7
th(TCH-TF)
TFRM
Figure 27. Serial-Port Receive Timing in TDM Mode
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