SMJ320LC549 Datasheet, PDF (24/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
ready timing for externally generated wait states
timing requirements for externally generated wait states [H = 0.5 t_c(CO)]^† (see Figure 10, Figure 11,
Figure 12, and Figure 13)
549-60
MIN MAX
UNIT
tsu(RDY)
Setup time, READY before CLKOUT low
7
ns
th(RDY)
tv(RDY)MSTRB
th(RDY)MSTRB
tv(RDY)IOSTRB
th(RDY)IOSTRB
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low^‡
Hold time, READY after MSTRB low^‡
Valid time, READY after IOSTRB low^‡
Hold time, READY after IOSTRB low^‡
2
ns
4H–10* ns
4H+1*
ns
5H–10* ns
5H*
ns
tv(MSCL)
Valid time, MSC low after CLKOUT low
–1*
6 ns
tv(MSCH)
Valid time, MSC high after CLKOUT low
–1*
6 ns
*Not production tested.
† _{The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by}
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ _{These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.}
CLKOUT
A[15:0]
READY
tsu(RDY)
th(RDY)
tv(RDY)MSTRB
MSTRB
th(RDY)MSTRB
MSC
tv(MSCL)
tv(MSCH)
Wait States
Generated Internally
Wait State
Generated
by READY
Figure 10. Memory Read With Externally Generated Wait States
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