SMJ320LC549 Datasheet, PDF (37/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

buffered serial port receive timing
SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
timing requirements (see Figure 24)
tc(SCK) Cycle time, serial port clock
tf(SCK)
Fall time, serial port clock
tr(SCK)
Rise time, serial port clock
tw(SCK) Pulse duration, serial port clock low/high
tsu(BFSR) Setup time, BFSR before BCLKR falling edge (see Note 2)
th(BFSR) Hold time, BFSR after BCLKR falling edge (see Note 2)
tsu(BDR) Setup time, BDR before BCLKR falling edge
th(BDR) Hold time, BDR after BCLKR falling edge
*Not production tested.
† _{The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity.}
‡ _{First bit is read when BFSR is sampled low by BCLKR clock.}
NOTE 2: Timings for BCLKR and BFSR are given with polarity bits (BCLKP and BFSP) set to 0.
t_c(SCK)
t_w(SCK)
BCLKR
549-60
MIN
MAX
20*
†
4*
4*
6*
2
7* tc(SCK)–2*^‡
0.5*
7*
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
tf(SCK)
BFSR
t_h(BFSR)
t_su(BFSR)
t_w(SCK)
t_su(BDR)
tr(SCK)
t_h(BDR)
BDR
1
2
8/10/12/16
Figure 24. Buffered Serial Port Receive Timing
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