SMJ320LC549 Datasheet, PDF (41/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

serial-port transmit timing in TDM mode
SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)] (see Figure 28)
PARAMETER
549-60
MIN MAX
UNIT
th(TCH-TDV)
th(TCH-TDV)
td(TCH-TFV)
Hold time, TDX/TADD valid after TCLK rising edge, TCLK external
Hold time, TDX/TADD valid after TCLK rising edge, TCLK internal
Delay time, TFRM valid after TCLK rising edge TCLK ext^†
Delay time, TFRM valid after TCLK rising edge, TCLK int^†
–3.5*
ns
0.5*
ns
H – 3* 3H + 22*
ns
H – 3* 3H + 12*
td(TC-TDV)
Delay time, TCLK to valid TDX/TADD, TCLK ext
Delay time, TCLK to valid TDX/TADD, TCLK int
25*
ns
18*
*Not production tested.
† _{TFRM timing and waveforms shown in Figure 28 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is}
illustrated in the receive timing diagram in Figure 27.
timing requirements [H = 0.5t_c(CO)] (see Figure 28)
tc(SCK)
Cycle time, serial-port clock
tf(SCK)
Fall time, serial-port clock
tr(SCK)
Rise time, serial-port clock
tw(SCK)
Pulse duration, serial-port clock low/high
*Not production tested.
‡ _{When SCK is generated internally, this value is typical.}
§ _{The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching 1.}
549-60
MIN MAX
16H*^‡
§
6*
6*
8H*^‡
UNIT
ns
ns
ns
ns
TCLK
TDX
TADD
TFRM
tw(SCK)
tw(SCK)
tf(SCK)
tc(SCK)
B15
B0
td(TC-TDV)
tr(SCK)
B14
B13
B12 B8 B7
B2
B1
B0
th(TCH-TDV)
th(TCH-TDV)
td(TC-TDV)
A1
A2
A3 A7
td(TCH-TFV)
A0
td(TCH-TFV)
Figure 28. Serial-Port Transmit Timing in TDM Mode
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