SMJ320LC549 Datasheet, PDF (39/52 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SMJ320LC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS032B – OCTOBER 2002 – REVISED MAY 2003
buffered serial port transmit timing of internal frame and internal clock
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)] (see Figure 26)
PARAMETER
549-60
UNIT
MIN MAX
tc(SCK)
Cycle time, serial port clock, internal clock
62H* ns
td(BFSX)
Delay time, BFSX after BCLKX rising edge (see Notes 3 and 4)
0* 10* ns
td(BDX)
Delay time, BDX valid after BCLKX rising edge
11* ns
tdis(BDX)
Disable time, BDX after BCLKX rising edge
0*
5* ns
tdis(BDX)pcm Disable time, PCM mode, BDX after BCLKX rising edge
5* ns
ten(BDX)pcm Enable time, PCM mode, BDX after BCLKX rising edge
7*
ns
th(BDX)
Hold time, BDX valid after BCLKX rising edge
–3*
ns
tf(SCK)
Fall time, serial port clock
3.5* ns
tr(SCK)
Rise time, serial port clock
3.5* ns
tw(SCK)
Pulse duration, serial port clock low/high
6*
ns
*Not production tested.
NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined
depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.
4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.
BCLKX
t_c(SCK)
t_w(SCK)
tf(SCK)
BFSX
t_d(BFSX)
t_d(BFSX)
t_w(SCK)
tr(SCK)
t_d(BDX)
t_h(BDX)
t_dis(BDX)
BDX
1
2
8/10/12/16
Figure 26. Buffered Serial Port Transmit Timing of Internal Clocks and Internal Frames
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