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CD00161566 Datasheet, PDF (76/105 Pages) STMicroelectronics – nullMedium-density performance line ARM-based 32-bit MCU
Electrical characteristics
STM32F103x8, STM32F103xB
5.3.18
Note:
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 9.
It is recommended to perform a calibration after each power-up.
Table 46. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
VREF+
IVREF
fADC
fS(2)
fTRIG(2)
VAIN(3)
RAIN(2)
Power supply
Positive reference voltage
Current on the VREF input pin
ADC clock frequency
Sampling rate
External trigger frequency
fADC = 14 MHz
Conversion voltage range
External input impedance
See Equation 1 and
Table 47 for details
2.4
2.4
0.6
0.05
-
-
0 (VSSA or VREF-
tied to ground)
-
-
-
160(1)
-
-
-
-
-
-
3.6
VDDA
220(1)
14
1
823
17
VREF+
50
V
V
µA
MHz
MHz
kHz
1/fADC
V
k
RADC(2)
CADC(2)
Sampling switch resistance
Internal sample and hold
capacitor
tCAL(2) Calibration time
tlat(2)
Injection trigger conversion
latency
tlatr(2)
Regular trigger conversion
latency
tS(2)
tSTAB(2)
Sampling time
Power-up time
tCONV(2)
Total conversion time
(including sampling time)
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
-
-
1
-
-
8
5.9
83
-
-
0.214
-
-
3(4)
-
-
0.143
-
-
2(4)
0.107
-
17.1
1.5
-
239.5
0
0
1
1
-
18
14 to 252 (tS for sampling +12.5 for
successive approximation)
k
pF
µs
1/fADC
µs
1/fADC
µs
1/fADC
µs
1/fADC
µs
µs
1/fADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3.
In devices
connected
connected
delivered in VFQFPN
to
to
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4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 46.
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